A Full Digital Self-timed Clock Generation Scheme
نویسندگان
چکیده
A full digital self-timed clock generation scheme is developed, where multiple internal clocks are self-generated for each external request. The internal clock period is designed to be the critical path delay of the internal system at all operating environments. This scheme can be applied to time-multiplexed implementations, self-timed operation , and low-power applications.
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